Companies That Produce Asic Eda Tools For Digital System Design

Digital design flows with the technology of automation. The focus of this paper is serving various Electronic Design Automation (EDA) tools and software for different operating system and platforms. This paper has classified the EDA tools for every specific task. Hence in this research paper, the comparison of various EDA software development models has been carried out to calculate the performance of each model on behalf of some important features.

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SEU Journal of Science and Engineering, Vol. 11, No. 1, June 2017

* Corresponding Author: Md. Mydul Islam, Student, Electrical and Electronic Engineering, Green University of

Bangladesh, Dhaka, Bangladesh, Email: mydul@ieee.org

Survey on Electronic Design Automation Tools And Software

Md. Mydul Islam * , Faysal Al Mahmud, Md. Hasan Maruf, and

Md. Atiqul Islam

Department of Electrical and Electronic Engineering,

Green University of Bangladesh, Dhaka, Bangladesh.

Abstract

Digital design flows with the technology of automation. The focus of this paper is serving

various Electronic Design Automation (EDA) tools and software for different operating

system and platforms. This paper has classified the EDA tools for every specific task.

Hence in this research paper, the comparison of various EDA software development

models has been carried out to calculate the performance of each model on behalf of some

important features.

Keywords: Area, Crosstalk and Coupling Noise, Delay, Power Consumption, Yield,

and Manufacturability.

I. Introduction

As the growth of integrated circuit is

increasing exponentially; the need of

Electrical Design Automation is increased.

Some advanced geometric software was used

for implementing integrated circuit. But for

more complex circuit the geometric software

was not capable to maintain the layer limits

(Yogesh Dilip Save et al., 2013), so

performance became lower. For solving those

kinds of problems EDA software tools are

used as well. Many software companies are

working on EDA tools and analysis for more

features and better performances.

EDA involves a diverse set of software

algorithms and applications that are required

for the design of complex next generation

semiconductor and electronics products. The

increase in VLSI design complexity poses a

significant challenge to EDA; application

performance is not scaling effectively since

microprocessor performance gains have been

hampered due to increases in power and

manufacturability issues, which accompany

scaling. Digital systems are typically

validated by distributing logic simulation

tasks among huge compute farms for weeks at

a time. Yet, the performance of simulation

often falls behind, leading to incomplete

verification and missed functional bugs (Jan

Schmidt et al., 2014). It is indeed no surprise

that the semiconductor industry is always

seeking for faster simulation solutions.

This paper is based on the survey on EDA

tools and software where the free and open

source and proprietary source both platforms

for EDA tools are described in a comparative

way. Open-source EDA platforms have

proven to be critical to improving the quality

of EDA research by offering well-designed

reference algorithms, highly tuned coding

implementations, and real-world

experimental data. Instead, the proprietary

platform provides a feasible approach to focus

on a few key computing patterns and develop

highly efficient solutions for complex Circuit.

II. Electronic Design Automation

Electronic design automation (EDA) is a

category of software tools for designing

electronic systems such as printed circuit

boards and integrated circuits. The tools work

together in a design flow that chip designers

use to design and analyze entire

semiconductor chips. EDA tools are that kind

of software which takes deep challenges to

design the complex integrated circuit by

maintaining the characteristics of IC and

analyzing the performance of different

portion. EDA tools have system-level, high-

level, logic-level, and layout-level. It has its

own set of synthesis, verification, and analysis

toolset. (P.K. Agarwal et al., 1992). If the

outcomes of the design are total power, power

consumption, noise margin, timing diagram,

these tools help for calculating the errors and

actuating the desired findings.

III. Categories

EDA tools are categorized based on its

different functions like schematic entry, PCB

design, simulation, Gerber view, etc.

Maintaining all the features EDA tools has

two specific categories, (P.K. Agarwal et al.,

1992). one is Free and Open Source Software

(FOSS) and other one is Proprietary Software.

IV. Free and open source Software

Open and free source software means a

package of software where it can be used with

a free license.

Proprietary Software has much more

features and most of them can fill up

maximum demands of a user. On the other

hand, free software cannot provide all types of

facilities so a user needs to use different tools

for the different task. There a lot of free EDA

software with open source.

Some of them are used as Synthesis tools,

physical design tools, (L. Aigo et al., 1995).

FPGA tools and Simulator (Verilog and

VHDL).

Synthesis tools: Synthesis is the process of

translating the schematic and behavioral

VHDL descriptions of the design into a low-

level form suitable for the vendor place and

route tools. (L. Aigo et al., 1995). Most usable

synthesis tools are- PLA generators, gate-

array generators, gate-matrix generators,

compactors, routers, placement systems, pad-

frame generators, aligners, pitch matches,

ICARUS Verilog, VERILATOR, ghdl,

ChipVault, KiCad, Precision RTL, Leonardo

Spectrum.

1) PLA generators: PLAs are popular

because their generation can be automated,

which frees the designer from spending

valuable time creating random-logic gates.

Since the PLA generator fixes the physical

structure of the PLA, there arises the problem

of accommodating the designer's special

requirements (P.K. Agarwal et al., 1992).

The PLA is folded to reduce the area required

for the physical implementation.

2) Gate-matrix generator: A typical gate-

array is built from blocks that contain

unconnected transistor pairs, (M. Alidina et

al., 1994). although any simple component

will do. An array of these blocks combined

with I/O pads forms a complete integrated

circuit and offers a wide range of digital

electronic options (see Figure: 1). These

blocks are internally customized by

connecting the components to form various

logical operators such as AND, OR, NOT, and

so on.

SEU Journal of Science and Engineering, Vol. 11, No. 1, June 2017 21

Figure 1: Gate-Arrays

3) Gate matrix Generator: The gate

matrix is the next step in the evolution of

automatically generated layout from the high-

level specification. Like the PLA, this layout

has no fixed size; a gate matrix grows

according to its complexity. Like all regular

forms of layout, this one has its fixed aspects

and its customizable aspects. (M. Alidina et

al., 1994). In gate matrix layout the fixed

design consists of vertical columns of

polysilicon gating material. (M. Alidina et al.,

1994). The customizable part is the metal and

diffusion wires that run horizontally to

interconnect (P. Ashar et al., 1995) and form

gates with the columns. Figure 2 is an

example.

Figure 2: Gate matrix Generation: a) Original

circuit b) Translation c) Optimization d) Layout

generation.

4) Compactor: Compactor is a most

important tool in the synthesis process. One-

dimensional compaction uses information

about components and their connecting wires.

The wires that run perpendicular to the

direction of compaction link a set of

components into a single track that will adjust

together.

5) ICARUS Verilog: Icarus Verilog is a

software of digital analysis. Verilog is used as

simulation and synthesis tool (M. Bae et al.,

1998). It operates as a compiler, compiling

source code written in Verilog into some

target format.

For batch simulation, the compiler can

generate an intermediate form called VVP

assembly. This intermediate form is executed

by the "VVP'' command. For synthesis, the

compiler generates netlists in the desired

format.

6) KiCad: KiCad is an open source EDA

software for Windows, OSX, and Linux.

Create PCB circuits and synthesis.

Figure 3: KiCad interface

KiCad uses two separate types of library:

symbols (.lib) and footprints (. pretty) (M. Bae

et al., 1998). Symbols are used to draw the

schematic. Once symbols have been placed

into the schematic, footprints are assigned to

them, and then these are used to lay out the

circuit board.

Physical layout tools: Physical layout

tools are that kind of tools which actually used

for metal layout implementing of an IC and

make a netlist of connections. (Harinarayan V.

et al., 1996). There is a huge collection of the

free and open source physical layout tools of

different companies like Tanner, Magic layout

tools, MICROWIND, Alliance CAD Tools,

OCEAN, &NBSP, Irsim, Gtkwave, Electric,

Toped, Netgen, Dragon, SystemC, SPACE.

7) Tanner: Tanner is a most leading

software in physical layout tools. It earns a

very good reputation for its design, layout,

and verification of analog/mixed-signal

(AMS). Tanner Waveform Viewer provides

an intuitive multiple-window, multiple-chart

interface for easy viewing of waveforms and

data in highly configurable formats.

8) Magic Layout Tools: Magic is a mixed

signal type software.

Figure 4: Magic Layout Tools

It offers open source licenses for VLSI

engineers. Its core algorithm makes it more

popular and it is widely used in the whole

world.

This figure is taken, from Magic version 7.2.

(M. Bae et al., 1998). It shows off a number

of features of this software, including the cell

manager window, the tech manager window,

the toolbar, the console command-line entry

window, and pop-up dialog boxes.

9) MICROWIND: Microwind is a user-

friendly mixed signal EDA tools which also

has a plenty of uses (H. B. Bakoglu et

al.,1990).

Figure 5: Interface of MICROWIND

Microwind integrates traditionally

separated front-end and back-end chip design

SEU Journal of Science and Engineering, Vol. 11, No. 1, June 2017 23

into an integrated flow, accelerating the

design cycle and reduce design complexities.

10) Alliance CAD Tools: This software is

usually used for designing the flow from

VHDL up to layout, (VHDL Compilation and

Simulation, model checking and formal proof,

RTL (W. Athas et al., 1995), and Logic

synthesis, Data-Path compilation, macro-cells

generation, place and route, layout edition,

Netlist extraction (M. Bae et al.,1998), and

verification, Design rules checking. It is a

complete set of free CAD tools and portable

libraries for VLSI design. It includes a VHDL

(Barclay T. et al.,1990), compiler and

simulator, logic synthesis tools, and automatic

place and route tools. A complete set of

portable CMOS libraries is provided,

including a RAM generator, a ROM generator

and a data-path compiler (H. B. Bakoglu et

al.,1990).

11) Electric: Electric is mixed signal type

software for complex IC designing. It is a

sophisticated electrical CAD system that can

handle many forms of circuit design,

including custom IC layout (ASICs),

schematic drawing (N. Dutt et al., 1996),

hardware description language specifications,

and electro-mechanical hybrid layout.

12) FPGA tools and Simulator: These

tools are used for hardware modeling,

operator simulation, function simulation,

timing simulation, and visualization. Xilinx,

ISE™ WebPACK™ Software, Altera

Quartus® II Software are the most common

tools for FPGA (H. B. Bakoglu et al., 1990)

and Simulation. FIZZIM, FEDORA

electronic lab, GHDL VHDL simulator,

EMACS - text editor, TCE, C to Verilog

translation, GEDA project, KICAD (H. H.

Chen et al.,1995). XCIRCUIT, Fritzing,

QUCS are also the usable software for FPGA

and simulating.

13) ISE™ WebPACK™ Software: ISE®

WebPACK™ design software is the

industry´s only FREE, fully featured front-to-

back FPGA design solution for Linux,

Windows XP, and Windows 7. (N. Dutt et al.,

1996). It gives the features like Micro Blaze

Microcontroller System, design Preservation,

Project Navigator, CORE Generator,

Power Optimization ISE Simulator (ISim),

XST Synthesis, Timing Driven Place &

Route, SmartGuide, and SmartXplorer.

14) Altera Quartus® II: the company

Altera provides the Quartus® II software for

analysis and synthesis of HDL designs, (W. K.

Chen et al., 1993), which enables the

developer to compile their designs, perform

timing analysis, examine RTL diagrams,

simulate a design's reaction to different

stimuli, and configure the target device with

the programmer.

15) Fizzim: Runs on Windows, Linux, and

Apple, anything with java. Familiar Windows

look-and-feel. Visibility (on/off/only-non-

default) and color control on data and

comment fields. Multiple pages for complex

state machines. (Mumick I. S. et al., 1994),

"Output to clipboard" makes it easy to pull the

state diagram into given documentation.

16) Fedora: This software is actually

based on Linux operating system. Red-hat is

the sponsor of this tool. These tools for

Specific Integrated Circuit (ASIC), Design

Flow process. Among all these, Fedora users

benefit (for free) the experience of an

EDA/CAD team who has working knowledge

in the ASIC industry (Mumick I. S. et al.,

1994), This EDA/CAD team works closely

with upstream to provide Fedora users the

latest updates and enhancements brought

forward.

17) TCE: TCE is a toolset for designing

application-specific processors (ASP) based

on the Transport triggered architecture (TTA).

The toolset provides a complete co-design

flow from C programs down to synthesizable

VHDL and parallel program binaries.

Processor customization points include the

operations, and the interconnection network.

18) MultiSIM: Multisim is an industry

standard design/simulation software.

Multisim is an easy-to-use and graphical

simulation software. Engineers can run

simulations with virtual instruments, such as

an oscilloscope, that mimic how an engineer

would simulate in the real world. In

professional world engineers benefitted from

the visual-style of design and simulation,

which is highly advanced in terms of

accuracy. As schematics get more complex,

the design can naturally become difficult to

understand. But with Multisim, engineers can

handle and keep track of various functional

modules and their respective

interconnections.

Figure 6: MultiSIM Interface

V. Proprietary Software

Proprietary software is that kind of

software which is restricted to copyright,

share or distribute. This software can be

owned by an individual or a company that has

a license provided by the publisher. (Mumick

I. S. et al., 1994), They are typically clos ed-

source, meaning the developer does not

provide the source code to anyone outside the

company. Proprietary programs are licensed

to end users under specific terms defined by

the developer or publisher. These terms often

restrict the usage, distribution, and

modification of the software.

Most commercial software is proprietary

because it gives the developer a competitive

advantage.

Synopsys, Cadence, Mentor Graphics are

most reliable and commonly used premium

EDA tools in the world of IC complexity.

TERADYNE, Altera, Spansion, Numonyx,

Lattice, Scheme-it, CircuitLab, KtechLab,

Target 3001! EDWinXP, TINA, NI Circuit

Design Suite, CometCAD, CADint, ViewPlot

are also the proprietary software.

1) Synopsys: Synopsys is a VLSI

Debugging software. The application of this

software is a specification of the integrated

circuit, including logic synthesis, behavioral

synthesis, place, and route, static timing

analysis, formal verification, HDL, SystemC,

System Verilog/Verilog, VHDL simulation as

well as transistor level circuit simulation. The

simulators include development and

debugging environments which assist in the

design of the logic for chips and computer

systems.

2) Cadence: Cadence enhances

schematic editing efficiency of even complex

designs through hierarchical and variant

design capabilities.

SEU Journal of Science and Engineering, Vol. 11, No. 1, June 2017 25

Figure 7: Cadence Software Interface

It integrates with a CIS to promote the use

of preferred, current parts and accelerates the

design process and reduces project costs.

Besides Cadence is a leading EDA and

System Design Enablement provider

delivering tools, software, and IP to help you

build great products.

3) Mentor Graphics: Mentor Graphics is

a leader in electronic design automation. The

application of mentor graphics integrated

circuit layout, IC place and route, IC

Verification, IC Design for Manufacturing,

(Harinarayan V. et al., 1996), Schematic

editors for electronic schematics.

Figure 8: Mentor Graphics

4) TCAD Silvaco: Silvaco is a leading

EDA provider of software tools used for

Figure 9: TCAD Silvaco Interface

process and device development and for

analog/mixed-signal, power IC, and memory

design. Silvaco delivers a full TCAD to

signoff flow for vertical markets including

displays, power electronics, optical devices,

radiation, soft error reliability, advanced

CMOS process and IP development. Silvaco

complements its design tools with a

comprehensive portfolio of processor and

networking IP for the automotive cloud-based

enterprise level IP management solution.

5) Minimos: Minimos is a two- and

three-dimensional device and circuit

simulator, integrated with a TCAD

framework. MINIMOS is a software tool for

the numerical simulation of field-effect

transistors such as silicon bulk and SOI

MOSFETs, and gallium arsenide MESFETs.

The fundamental semiconductor equations,

consisting of Poisson's equation and two

carrier continuity equations, are solved

numerically in two- and three-dimensional

domains. Finite differences are employed for

space discretization and the Backward Euler

method (S. Selberherr et al., 1987) for time

discretization. MINIMOS generates an

adaptive grid and has an automatic time step

control.

Figure 10: Minimos Software Interface

6) Autodesk EAGLE: Autodesk expands

its cadre of using digital tools by acquiring

CAD Soft EAGLE, a popular easy to use

print circuit board (PCB) site.

This Software assures that how to learn

people to making PCB design more affordable

and accessible with the new designing method

for EAGLE PCB design software. Eagle more

popular for simulation with spice system like

LTspice and PCB designing like as PCBSim.

Mainly it is a schematic type design and runs

on POSIX style system. It supported all kinds

of the platform like Mac, Linux, and

Windows.

Figure 11: Autodesk Eagle

7) PCB Investigator: PCB Investigator

is a layout designing tool which improves

Figure 12: PCB Investigator

the development process and makes more

simple and secure of layout design.

The CAD Software created is extremely

easy to use and user-friendly. PCB

Investigator is provided by EasyLogix

Schindler & Schill GmbH. PCB Investigator

Scripts and PCB-Investigator C# extension

scripts are automating E-CAD related tasks.

The feature of Import/Export ODB++,

Gerber274x, and Excellon with PCB-

Investigator (Ansgar Wego et al., 2001).

These data formats work with all CAD design

tools e.g. Mentor Graphics, Cadence etc

VI. Comparative Analysis

Choosing the best type of software depends

on user business needs and objectives. The

best way to compare is to look at some of the

biggest differences between the two types-

SEU Journal of Science and Engineering, Vol. 11, No. 1, June 2017 27

Table 1: Compare between software based on

user needs and objectives.

Open source and

free software

Creators are

the ones that

generally

handle the

development

and fixes,

meaning it is

under their

discretion

Development is

handled through

'mass

collaboration'.

As a result,

development

and fixes usually

continue as long

as the

community is

active

Usually have

a dedicated

FAQ,

manuals, and

options to

contact

someone.

There are not

many support

options such as

a dedicated and

organized FAQ

or contacting

someone may

not be available.

Tends to

have only as

much

flexibility as

the creators

intended.

Can modify the

functions and

even add

community

created

modifications or

features to suit

your needs

Price model

includes the

right to use

the software.

No cost

associated with

the software

Can give

maximum

features and

a better

interface for

a user.

All the features

cannot be given

in one.

Most of the

time it

provides

higher

accuracy.

The outcomes

are not totally

accurate all the

time.

Always

performs

with better

efficiency.

Remains in

average level.

VII. Conclusion

In the age of technology and automation,

software is being used more and more in day-

to-day tasks. No matter what type of uses the

software has, there are two overarching types:

premium and open source. This survey

actually focused on the two types of software

and discussed the topics of development,

support, flexibility, and cost.

The premium software holds the source

code safe and encrypted. Meaning, the user

can't copy, modify, or delete parts of the code

without some type of consequence. It can go

from voiding the warranty to even legal

repercussions.

Open source software is completely

opposite. It allows users to copy, modify, or

delete parts of the code under their own

discretion. The user is able to use functions of

the open source on their own program with no

consequence.

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ResearchGate has not been able to resolve any citations for this publication.

In this paper, we discuss the implementation of Open Source CAD (Oscad) [1], a complete EDA tool for Electronics and Electrical engineers. The paper illustrates the use of Oscad for circuit design, simulation and PCB design. It also gives implementation details of an in-house developed circuit simulator, Scilab based Mini Circuit Simulator (SMCSim), available in Oscad. The simulator can provide the system of equations for the circuit under test. This feature is unique to Oscad. The paper presents two examples to show the capabilities of Oscad.

Mazhar Alidina
José C. Monteiro
Srinivas Devadas
Marios C. Papaefthymiou

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be "turned off" in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing...

It is known that EDA tools produce results of different quality dependent on seemingly neutral details in the input. We bring further results in this direction, which show that the differences can impair any quantitative comparisons of the tools. To gain qualitative insight, we present a stochastic model of result quality based on Gaussian Mixtures. We show on three case studies how these models help to evaluate and improve EDA algorithms.

Ansgar Wego
Glock Hans-Walter
Lienhard Pagel
Stefan Richter

In this paper, four thermo-pneumatic driving concepts for volume actuators based on printed circuit board technology (PCB) are presented. Several experimental measurements have been realised to quantify the power consumption and the behaviour of the actuators for different duty cycles and frequencies. This allows an evaluation of the concepts with respect to an application in micropumps or active valves. Simulations using the finite integration technique (FIT) have been accomplished to calculate the resulting chamber temperature of an actuator if a certain amount of heating power is dissipated in the chamber. The results are validated with measurement data.

Tom Barclay
Robert Barnes
Jim Gray
Prakash Sundaresan

This paper describes a parallel database load prototype for Digital's Rdb database product. The prototype takes a dataflow approach to database parallelism. It includes an explorer that discovers and records the cluster configuration in a database, a client CUI interface that gathers the load job description from the user and from the Rdb catalogs, and an optimizer that picks the best parallel execution plan and records it in a web data structure. The web describes the data operators, the dataflow rivers among them, the binding of operators to processes, processes to processors, and files to discs and tapes. This paper describes the optimizer's cost-based hierarchical optimization strategy in some detail. The prototype executes the web's plan by spawning a web manager process at each node of the cluster. The managers create the local executor processes, and orchestrate startup, phasing, checkpoint, and shutdown. The execution processes perform one or more operators. Data flows among the operators are via memory-to-memory streams within a node, and via web-manager multiplexed tcp/ip streams among nodes. The design of the transaction and checkpoint/restart mechanisms are also described. Preliminary measurements indicate that this design will give excellent scaleups.

Martin Thurner
Siegfried Selberherr

An accurate three-dimensional simulaton program for MOSFET devices has been developed by extending MINIMOS (vers. 4) in 31). The physical model is based on the 'hot-electron transport-model', which includes the Poisson equation, the continuity equations and a selfconsistent set of equations for the currents, mobilities and carrier-temperatures. The standard finite difference discretization and the SOR (successive over relaxation) method are utilized to reduce computational time and memory requirements. Adaptive grid refinement is used to equidistribute the discretization errors. Three-dimensional effects like threshold shift for small channel devices, channel narrowing and the accumulation of carriers at the channel edge have been successfully modeled. Our analyses make clear that three-dimensional calculations are most important for accurate device modeling.

Shantanu Dutt
Wenyong Deng

Move-based iterative improvement partitioning methods such as the Fiduccia-Mattheyses (FM) algorithm and Krishnamurthy's Look-Ahead (LA) algorithm are widely used in VLSI CAD applications largely due to their time efficiency and ease of implementation. This class of algorithms is of the "local improvement" type. They generate relatively high quality results for small and medium size circuits. However, as VLSI circuits become larger, these algorithms are not so effective on them as direct partitioning tools. We propose new iterative-improvement methods that select cells to move with a view to moving clusters that straddle the two subsets of a partition into one of the subsets. The new algorithms significantly improve partition quality while preserving the advantage of time efficiency. Experimental results on 25 medium to large size ACM/SIGDA benchmark circuits show up to 70% improvement over FM in cutsize, with an average of per-circuit percent improvements of about 25%, and a total cut improvement of about 35%. They also outperform the recent placement-based partitioning tool Paraboli and the spectral partitioner MELO by about 17% and 23%, respectively, with less CPU time. This demonstrates the potential of iterative improvement algorithms in dealing with the increasing complexity of modern VLSI circuitry